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The Pentium II brand refers to Intel's sixth-generation microarchitecture ("P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB L2 cache), the Pentium II featured an improved version of the first ''P6''-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to Pentium Pros. In early 1999, the Pentium II was superseded by the almost identical Pentium III, which basically only added SSE instructions to the CPU. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end workstations and the Pentium II Xeon line for servers and high-end workstations. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache (from 512 KB to 2048 KB), a 100 MT/s FSB, a different physical interface (Slot 2), and support for symmetric multiprocessing. ==Overview== The Pentium II microprocessor was largely based upon the microarchitecture of its predecessor, the Pentium Pro, but with some significant improvements. Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a slot-based module rather than a CPU socket. The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side, sometimes using its own fan.〔Pabst, Thomas. (Intel's Slot 1 CPUs Uncovered ), Tom's Hardware, May 3, 1998.〕 This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled back-side bus. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, the smallest cache size was increased to 512 KB from the 256 KB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yields, allowing Intel to introduce the Pentium II at a mainstream price level.〔Pabst, Thomas. (The Intel Pentium II ('Klamath') CPU ), Tom's Hardware, March 1, 1997.〕〔Lal Shimpi, Anand. (Intel Pentium II ), Anandtech, May 30, 1997.〕 This arrangement also allowed Intel to easily vary the amount of L2 cache, thus making it possible to target different market segments with cheaper or more expensive processors and accompanying performance levels. Intel notably improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The Pentium II went to 32 KB of L1 cache, double that of the Pentium Pro, as well. The Pentium II was also the first P6-based CPU to implement the Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX.〔 The Pentium II was basically a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, and multimedia applications. Combined with the larger L1 cache and improved 16-bit performance, the slower and cheaper L2 cache's performance impact was reduced. General processor performance was increased while costs were cut.〔〔Pabst, Thomas. (The Empire Strikes Back: Intel's Pentium II CPU ), Tom's Hardware, April 30, 1997.〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Pentium II」の詳細全文を読む スポンサード リンク
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